The Intel 8088 and 8086 Processor’s Instruction Prefetch Circuitry

Cache prefetching is what permits processors to have information and/or directions prepared to be used in a quick native cache relatively than having to attend for a fetch request to trickle by to system RAM and again once more. The Intel 8088  (and its huge brother 8086) processor was among the many first microprocessors to implement (instruction) prefetching in {hardware}, which [Ken Shirriff] has analyzed primarily based on die photographs of this well-known processor. This follows last year’s deep-dive into the 8086’s prefetching {hardware}, with (unsurprisingly) many similarities between these two microprocessors, in addition to a couple of variations which might be principally because of the 8088’s cut-down 8-bit information bus.

Whereas the 8086 has 3 16-bit slots within the instruction prefetcher the 8088 will get 4 slots, every 8-bit. The prefetching {hardware} is a part of the Bus Interface Unit (BIU), which successfully decouples the precise processor (Execution Unit, or EU) from the system RAM. Whereas earlier MPUs can be totally deterministic, with directions being loaded from RAM and subsequently executed, the 8086 and 8088’s prefetching meant that such assumptions not had been true. The added options within the BIU additionally meant that the instruction pointer (IP) and associated registers moved to the BIU, whereas the ringbuffer logic across the queue needed to by some means hold the queueing and pointer offsets into RAM working accurately.

Regardless that as of late CPUs have way more difficult, multi-level caches which might be measured in kilobytes and megabytes, it’s fascinating to see the place all of it started, with just some bytes and comparatively straight-forward {hardware} logic that you simply simply observe beneath a microscope.